The present invention relates to a semiconductor element suited for integration with a high density and a semiconductor memory device implemented by using the same.
Heretofore, polycrystalline silicon transistors have been used as elements for constituting a static random access memory device (referred to as SRAM in abbreviation). One of the relevant prior art techniques is described in T. Yamanaka et al: IEEE International Electron Device Meeting, pp. 477-480 (1990). By making the most of polycrystalline silicon transistors, integration density of the integrated circuit can be enhanced, the reason for which can be explained by the fact that the polycrystalline silicon transistor can be formed in stack or lamination atop a conventional bulk MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) formed on a surface of a semiconductor substrate with an insulation film being interposed between the polycrystalline silicon transistor and the bulk MOSFET. In the SRAM, implementation of a memory cell for one bit requires four bulk MOSFETs and two polycrystalline silicon transistors. However, because the polycrystalline silicon transistors can be stacked atop the bulk MOSFETs, a single memory cell of the SRAM can be implemented with an area which substantially corresponds to that required for the bulk MOSFETs.
As another preceding technique related to the invention, there may be mentioned a single-electron memory described in K. Nakazato et al: Electronics Letters, Vol. 29, No. 4, pp. 384-385 (1993). It is reported that a memory could have been realized by controlling electron on a one-by-one basis. It is however noted that the operation temperature is as very low as on the order of 30 mK.
As a further prior art technique related to the invention, there may be mentioned one which is directed to the study of RTN (Random Telegraph Noise) of MOSFET, as is disclosed in F. Fang et al: 1990 Symposium on VLSI Technology, pp. 37-38 (1990). More specifically, when a drain current of a MOSFET is measured for a predetermined time under the constant-voltage condition, there makes appearance such phenomenon that state transition takes place at random between a high-current state and a low-current state. This phenomenon is referred to as the RTN, a cause for which can be explained by the capture or entrapping of a single electron in a level node existing at an interface between silicon (Si) and silicon oxide (SiO2) and the release therefrom, whereby the drain current undergoes variations. However, the RTN remains only as a subject for a fundamental study concerning the current noise in the MOSFET, and any attempt or approach for positively making use of the RTN in practical applications has not been reported yet at all.
At present, the technology for processing a semiconductor integrated circuit with high fineness has developed up to such a level where any attempt for realization of higher fineness will encounter difficulty. Even if it is possible technologically, there will then arise a problem that intolerably high cost is involved due to the necessity for much sophisticated technique. Under the circumstances, a great demand exists for a fundamentally novel method of enhancing the integration density in the fabrication of semiconductor integrated circuits instead of relying on a method of implementing the semiconductor elements constituting the semiconductor integrated circuit simply by increasing the fineness thereof.
On the other hand, the polycrystalline silicon transistor known heretofore is basically equivalent to a variable resistor element in the respect that resistance between a source and a drain of the polycrystalline silicon transistor can be controlled by a gate voltage. Consequently, implementation of a memory cell of a SRAM requires as many as six semiconductor elements inclusive of the conventional MOSFETs formed in a silicon substrate.
By contrast, in the case of a DRAM (Dynamic Random Access Memory), information or data of one bit can be stored in a memory cell constituted by one MOSFET and one capacitor For this reason, the DRAM enjoys reputation as a RAM device susceptible to implementation with the highest integration density. However, because the DRAM is based on such a scheme that electric charge is read out onto a data wire of which capacitance is non-negligible, the memory cell thereof is required to have capacitance on the order of several ten fF (femto-Farads), which thus provides a great obstacle to an attempt for further increasing fineness in implementation of the memory cells.
By the way, it is also known that a nonvolatile memory device such as a flash EEPROM (Electrically Erasable and Programmable Read-Only Memory) can be realized by employing MOSFETs each having a floating gate and a control gate. Further, as a semiconductor element for such a nonvolatile memory device, there is known MNOS (Metal Nitride Oxide Semiconductor) element. The MOOS is designed to store charge at interface between a SiO2-film and a Si3N4-film instead of the floating gate of the flash EEPROM. Although the use of the MOSFET equipped with the floating gate or the MNOS element is certainly advantageous in that one-bit data can be held or stored by one transistor over an extended time span, a lot of time is required for the rewriting operation because a current to this end has to flow through the insulation film, whereby the number of times the rewriting operation can be performed is limited to about 100 millions, which in turn gives rise to a problem that limitation is imposed to the applications which the nonvolatile memory device can find.
On the other hand, the one-electron memory device discussed in the Nakazato et al""s article mentioned hereinbefore can operate only at a temperature of cryogenic level, presenting thus a problem which is very difficult to cope with in practice. Besides, a cell of the single-electron memory is comprised of one capacitor and two active elements, which means that a number of the elements as required exceeds that of the conventional DRAM, to a further disadvantage.
As will be appreciated from the forgoing, there exists a great demand for a semiconductor element which requires no capacitance elements, differing from that for the DRAM and which can exhibit stored function by itself in order to implement a memory of higher integration density than the conventional one without resorting to the technique for implementing the memory with higher fineness.
In the light of the state of the art described above, it is an object of the present invention to provide an epoch-making semiconductor element which allows a semiconductor memory device to be implemented with a lesser number of semiconductor elements and a smaller area and which per se has data or information storing capability while requiring no cooling at a low temperature such as cryogenic level.
Another object of the present invention is to provide a semiconductor memory device which can be implemented by using the semiconductor elements mentioned above.
A further object of the invention is to provide a data processing apparatus which includes as a storage the semiconductor memory device mentioned above.
For achieving the above and other objects which will become apparent as description proceeds, it is taught according to a basic technical concept underlying the invention that capacitance between a gate and a channel of a semiconductor field-effect transistor element is set so small that capture of a single carrier (electron or hole) by a trap level can definitely and discriminately detected as a change in the current of the semiconductor field-effect transistor element. More specifically, correspondences are established between changes in a threshold value of the semiconductor field-effect transistor element as brought about by capture of a carrier in the trap and releasing therefrom and digital values of logic xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, to thereby impart to the semiconductor field-effect transistor element a function or capability for storing data or information even at a room temperature.
Thus, according to a first aspect of the present invention in its most general sense thereof, there is provided a semiconductor element which includes a source region constituting a source of the semiconductor element, a drain region constituting a drain of the semiconductor element, an effective channel region provided between the source region and the drain region for interconnection thereof, a gate electrode connected to the channel region through a gate insulation film interposed between the gate electrode and the channel region, and a level node formed between the source region and the drain region in the vicinity of a current path in the channel region for capturing at least one carrier, wherein effective capacitance (which will be elucidated later on) between the gate electrode and the effective channel region is set so small as to satisfy a condition given by the following inequality expression:
1/Cgc greater than kT/q2 
where Cgc represents the effective capacitance, k represents Boltzmann""s constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron (refer to FIGS. 1A-1D).
According to another aspect of the present invention, there is provided a semiconductor element which includes a source region and a drain region is connected to the source region through a channel region interposed therebetween, a gate electrode connected to the channel region through a gate insulation film interposed between the gate electrode and the channel region, at least one carrier confinement region formed in the vicinity of the channel region for confining a carrier, and a potential barrier existing between the carrier confinement region and the channel region, wherein effective capacitance between the gate electrode and the effective channel region is set so small as to satisfy a condition given by the following inequality expression:
1/Cgc greater than kT/q2 
where Cgc represents the effective capacitance, k represents Boltzmann""s constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron (refer to FIGS. 10A, 10B).
According to yet another aspect of the present invention, there is provided a semiconductor element which includes a source region constituting a source of the semiconductor element, a drain region constituting a drain of the semiconductor element, the source region being connected to the drain region through a channel region interposed therebetween, a gate electrode connected to the channel region through a gate insulation film interposed between the gate electrode and the channel region, at least one carrier confinement region formed in the vicinity of the channel region for confining a carrier, and a potential barrier existing between the carrier confinement region and the channel region, wherein a value of capacitance between the channel region and the carrier confinement region is set greater than capacitance between the gate electrode and the carrier confinement region, and wherein total capacitance existing around the carrier confinement region is so set as to satisfy a condition given by the following inequality expression:
q2/2Ctt greater than kT 
where Ctt represents the total capacitance, k represents Boltzmann""s constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron (refer to FIGS. 10A, 10B).
At this juncture, it is important to note that with the phrase xe2x80x9ctotal capacitance (Ctt) means a total sum of capacitances existing between the carrier confinement region and all the other electrodes than the gate electrode.
In order to increase the number of times the semiconductor memory element can be rewritten, it is required to suppress to a possible minimum degradation of a barrier (insulation film) existing between the channel region and the carrier confinement region.
In view of the above, there is provided according to a further aspect of the invention a semiconductor element which includes a source region constituting a source of the semiconductor element, a drain region constituting a drain of the semiconductor element, the source region being connected to the drain region through a channel region interposed therebetween, a gate electrode connected to the channel region through a gate insulation film interposed between the gate electrode and the channel region, at least one carrier confinement region formed in the vicinity of the channel region for confining a carrier, the confinement region being surrounded by a potential barrier, storage of information being effectuated by holding a carrier in the carrier confinement region, and a thin film structure having a thickness not greater than 9 nm and formed of a semiconductor material in an insulation film intervening between the channel region and the carrier confinement region (refer to FIGS. 17A, 17B).
For better understanding of the present invention, the underlying principle or concept thereof will have to be elucidated in some detail.
In a typical mode for carrying out the invention, a polycrystalline silicon element (see e.g. FIGS. 1A-1D) is imparted with such characteristic that when potential difference between the gate and the source thereof is increased and decreased repetitively within a predetermined range with a drain-source voltage being held constant, conductance between the source and the drain exhibits a hysteresis even at a room temperature (see FIG. 2).
More specifically, referring to FIG. 2 of the accompanying drawings, when the gate-source voltage is swept vertically between a first voltage Vg0 (0 volt) and a second voltage Vg1 (50 volts), the drain current of the polycrystalline silicon element exhibits hysteresis characteristic. This phenomenon has not heretofore been known at all but discovered experimentally first by the inventors of the present application. The reason why such hysteresis characteristic can make appearance will be explained below.
FIG. 4A shows a band profile in a channel region of a semiconductor device shown in FIGS. 1A-1D in the state where the gate-source voltage Vgs is zero volt. A drain current flows in the direction perpendicular to the plane of the drawing. For convenience of discussion, it is assumed in the following description that the drain-source voltage is sufficiently low when compared with the gate voltage, being however understood that the observation mentioned below applies equally valid even in the case where the drain-source voltage is high.
Now referring to FIG. 4A, there is formed in a channel (3) of polycrystalline silicon a potential well of low energy between a gate oxide film (5) and a peripheral SiO2-protection film (10). In this case, energy level (11) of a conduction band in the channel region (3) which may be of p-type or of i-type (intrinsic semiconductor type) or n-type with a low impurity concentration is sufficiently high when compared with energy level of a conduction band in a n-type source region of a high impurity concentration or Fermi level (12) in a degenerate n-type source region of a high impurity concentration. As a consequence, there exist no electrons within the channel (3). Thus, no drain current can flow.
Further, a trap level (7) exists in the vicinity of the channel (3), which can capture or trap carriers such as electrons. As levels which partake in forming the trap level, there are conceivable a level extending to a grain or a level of group of grains (crystal grains in the channel regions of polycrystalline silicon) themselves which are surrounded by a high barrier, level internally of the grain, level at a Sixe2x80x94SiO2 interface (i.e., interface between the channel region (3) and the gate oxide film (5)), level inside the gate oxide film (5) and others. However, it is of no concern which of these levels forms the trap level. Parenthetically, even after the experiments conducted by the inverters, it can not be ascertained at present by which of the aforementioned levels the carriers or electrons are trapped in actuality. Of the levels mentioned above, energy in the trap level (7) which plays a role in realizing the hysteresis characteristic mentioned above is sufficiently higher than the Fermi level (12) in the source region (1). Accordingly, no electrons exist in the trap level (7). At this juncture, it should be added that although the trap level is shown in FIGS. 4A-4C as existing within the gate oxide film, the trap level need not exist internally of the oxide film. It is only necessary that the trap level exists in the vicinity of the channel.
As the potential difference Vgs between the gate (4) and the source (1) is increased from zero volt to the low threshold voltage Vl, potential in the channel region (3) increases. Consequently, as compared with the initial energy level of the channel region (3) in the state where the potential difference Vgs is zero (refer to FIG. 4A), the potential of the channel region (3) for electrons becomes lower under the condition that the potential difference Vgs is higher than zero volt and lower than the low threshold voltage Vl. When the gate-source potential difference Vgs has attained the low threshold voltage Vl, the Fermi level in the source region (1) approaches to the energy level in the conduction band of the channel region (3) (with a difference of about kT, where k represents Boltzmann""s constant and T represents operating temperature in Kelvin). Consequently, electrons are introduced into the channel region (3) from the source. Thus, a current flow takes place between the drain and the source.
When the gate voltage is further increased, the number of electrons within the channel region (3) increases correspondingly. However, when the potential difference Vgs has reached a capture voltage Vg1, energy of the trap level (7) approaches to the Fermi level (12), whereby at least one electron is entrapped or captured by the trap level (7) because of distribution of electrons under the influence of thermal energy of those electrons which are introduced from the source region (1). At that time, since the level of the trap (7) is sufficiently lower than potentials of the gate oxide (5) and peripheral SiO2-protection film (10), the electron captured by the trap level (7) is inhibited from migration to the gate oxide film (5) and the peripheral SiO2-protection film due to thermal energy of electron. Besides, because a grain boundary of high energy of the polycrystalline silicon channel region (3) exists in the vicinity of the trap level (7), for example, at the Sixe2x80x94SiO2 interface, the electron captured by the trap level (7) can not move from the trap level (refer to FIG. 4C). However, since the other electrons can move, the drain current continues to flow.
In this way, once a single electron is entrapped or captured by the trap level (7), the threshold voltage of the polycrystalline silicon semiconductor element shown in FIGS. 1A-1D changes from the low threshold voltage Vl to the high threshold voltage Vh, the reason for which will be explained below.
When the gate-source potential difference Vgs is lowered from the state shown in FIG. 4C within the range of Vh less than Vgs less than Vg1, the number of electrons within the channel region (3) is decreased. However, in general, a high energy region exists in the periphery of the trap level (7). Accordingly, the electron captured by the trap level (7) remains as it is (refer to FIG. 5A).
When the gate voltage is further lowered to a value at which the potential difference Vgs attains the high threshold voltage Vh, the Fermi level (12) of the source region (1) becomes different from the energy level of the conduction band of the channel (3) by ca. kT, as a result of which substantially all of the electrons within the channel disappear (see FIG. 5B). Consequently, the drain current can flow no more. However, the threshold voltage Vh at which no drain current flow becomes higher than the low threshold voltage Vl by a voltage corresponding to the charge of electron captured in the trap level (7).
Further, by lowering the gate-source potential difference Vgs to a value where the potential difference Vgs becomes equal to zero, potential in the peripheral high-energy region of the trap level (7) becomes lower in accompanying the lowering of the gate voltage, which results in that the electron captured by the trap level (7) is released to the region of low energy through tunneling under the effect of the electric field (refer to FIG. 5C).
Subsequently, the gate-source potential difference Vgs is again increased for the vertical sweeping. By repeating this operation, hysteresis can be observed in the drain current-versus-gate voltage characteristic owing to trapping and release of the electron.
In this conjunction, the inventors have discovered that the hysteresis characteristic mentioned above appears only when the capacitance between the gate and the channel is small. Incidentally, the experiment conducted by the inventors shows that although a semiconductor element having a gate length and a gate width each of 0.1 micron can exhibit the aforementioned hysteresis characteristic, a semiconductor element whose gate length and gate width are on the order of 1 (one) micron is incapable of exhibiting such hysteresis characteristic.
Thus, it must be emphasized that smallness of the capacitance Cgc between the gate electrode and the channel region is indispensable for the aforementioned hysteresis characteristic to make appearance, the reason for which may be explained as follows. There exists between an amount of charge Qs stored in the trap level and a change xcex94Vt (=Vhxe2x88x92Vl) in the threshold value or voltage the following relation:
xcex94Vt=Qs/Cgcxe2x80x83xe2x80x83(1) 
where Cgc represents capacitance between the gate and an effective channel. With the phrase xe2x80x9ceffective channelxe2x80x9d, it is intended to mean a region of the channel which restrictively regulates magnitude of a current flowing therethrough and which corresponds to a region of highest potential energy in the current path. Thus, this region may also be termed a bottle-neck region. In order to make use of the aforementioned hysteresis characteristic as the memory function, it is necessary that the state in which the threshold value is high (Vh) and the state where the threshold value is low (Vl) can definitely and discriminatively be detected as a change in the drain current. In other words, difference between the threshold values Vh and Vl has to be clearly or definitely sensed in terms of a difference or change appearing in the drain current. The conditions to this end can be determined in the manner described below. In general, the drain current Id of a MOS transistor having a threshold value Vt can be represented in the vicinity of the threshold value by the following expression:
Id=Axc2x7exp[q(Vgsxe2x88x92Vt)/(kT)]xe2x80x83xe2x80x83(2) 
where A represents a proportional constant, q represents charge of an electron, Vgs represents a gate-source voltage of the MOS transistor, Vt represents the threshold voltage, k represents Boltzmann""s constant and T represents an operating temperature in degree Kelvin. Thus, when Vt=Vh, the drain current is given by
Idh=Axc2x7exp[q(Vgsxe2x88x92Vh)/(kT)]xe2x80x83xe2x80x83(3) 
while when Vt=Vl, the drain current is given by
Idl=Axc2x7exp[q(Vgsxe2x88x92Vl)/(kT)]xe2x80x83xe2x80x83(4) 
Thus, ratio between the drain currents in the state where Vt=Vh and the state Vt=Vl can be determined as follows:
Idl/Idh=exp[q(Vhxe2x88x92Vl)/(kT)]xe2x80x83xe2x80x83(5) 
Thus, it can be appreciated that in order to make it possible to discriminate the two states mentioned above from each other on the basis of the drain currents as sensed, it is necessary that the drain current ratio Idl/Idh as given by the expression (5) is not smaller than the base e (2.7) of natural logarithm at minimum, and for the practical purpose, the current ratio of concern should preferably be greater than xe2x80x9c10xe2x80x9d (ten) inclusive. On the condition that the drain current ratio is not smaller than the base e of natural logarithm, the following expression holds true.
xcex94Vt(=Vhxe2x88x92Vl) greater than kT/qxe2x80x83xe2x80x83(6) 
Thus, from the expression (1), the following condition has to be satisfied.
Qs/Cgc greater than kT/qxe2x80x83xe2x80x83(7) 
In order that the capture of a single electron can meet the current sense condition mentioned above, it is then required that the following condition be satisfied.
q/Cgc greater than kT/qxe2x80x83xe2x80x83(8) 
From the above expression (8), it is apparent that in order to enable operation at a room temperature, the gate-channel capacitance Cgc should not exceed 6 aF (where a is an abbreviation of xe2x80x9catto-xe2x80x9d meaning 10xe2x88x9218). Incidentally, in the case of the semiconductor element having the gate length on the order of 1 micron, the gate-channel capacitance Cgc will amount to about 1 fF (where f is an abbreviation of xe2x80x9cfemto-xe2x80x9d meaning 10xe2x88x9215) and deviate considerably from the above-mentioned condition. By contrast, in the case of a semiconductor element fabricated by incarnating the teaching of the invention, the gate-channel capacitance Cgc is as extremely small as on the order of 0.01 aF, and it has thus been ascertained that a shift in the threshold value which can be sensed is brought about by the capture of only a single even electron at a room temperature.
Further, in the course of the experiment, the inventors have found that by holding the gate-source potential difference Vgs between zero volt and the voltage level Vg1, the immediately preceding threshold value can be held stably over one hour or more. FIG. 3 of the accompanying drawing shows the result of this experiment. More specifically, FIG. 3 illustrates changes in the drain current as measured under the condition indicated by a in FIG. 2 while holding the gate voltage to be constant. As can be seen in the figure, in the state of low threshold value, a high current level can be held, while in the state of high threshold value, a low current level can be held. Thus, by making use of the shift of the threshold value, it is possible to hold information or data, i.e., to store information or data, to say in another way. Further, by sensing the drain current in these states, it is possible to read out the data. Namely, the state in which the drain current is smaller than a reference value 13 may be read out as logic xe2x80x9c1xe2x80x9d data, while the state in which the drain current is greater than the reference value (13) may be read out as logic xe2x80x9c0xe2x80x9d (refer to FIG. 3).
On the other hand, data write operation can be effectuated by controlling the gate voltage. Now, description will be directed to the data write operation. It is assumed that in the initial state, the gate voltage is at the low level Vg0. By sweeping the gate voltage in the positive direction to the level Vg1 the threshold voltage at is set the high level Vh. With this operation, logic xe2x80x9c1xe2x80x9d of digital data can be written in the semiconductor element according to the invention. Subsequently, the gate voltage is swept in the negative direction to the zero volt level to thereby change the threshold voltage to the low level Vl. In this way, logic xe2x80x9c0xe2x80x9d of digital data can be written.
As will now be understood from the foregoing description, it is possible to write, hold and read the data or information only with a single semiconductor element. This means that a memory device can be implemented with a significantly smaller number of semiconductor elements per unit area when compared with the conventional memory device.
The semiconductor element according to the invention in which data storage is realized by capturing or entrapping only a few electrons in a storage node (which may also be referred to as the carrier confinement region or level node or carrier trap or carrier confinement trap, quantum confinement region or the like terms) can enjoy an advantage that no restriction is imposed on the number of times the data can be rewritten due to deterioration of the insulation film as encountered in a floating-gate MOSFET or restriction, if imposed, is relatively gentle.
It is however noted that in the case of the mode illustrated in FIGS. 1A-1D for carrying out the invention, relative positional relationship (i.e., relative distance) between the carrier trap level serving for the carrier confinement and the effective channel region serving as the current path is rather difficult to fix, involving non-ignorable dispersions of the threshold value change characteristic among the elements as fabricated.
As one of the measures for coping with the difficulty mentioned above, there is proposed another mode for carrying out the invention such as one illustrated in FIGS. 10A and 10B of the accompanying drawings in which the carrier confinement region (24) surrounded by a potential barrier is provided independently in the vicinity of a channel region (21). With this structure, the dispersion mentioned above can be reduced.
From the stand point of performance stability of the semiconductor element, it is preferred that dispersion of the voltage difference xcex94Vt between the high threshold voltage Vh and the low threshold voltage Vl among the semiconductor elements as fabricated should be suppressed to a possible minimum.
Certainly, the condition given by the expression (1) can apply valid when the capacitance Cgt between the gate region and the carrier confinement region as well as the capacitance C between the carrier confinement region and the channel region is sufficiently small. In the other cases than the above, the condition given by the following expression applies valid:
xcex94Vt=q/(1+Cgt/C)Cgcxe2x80x83xe2x80x83(9) 
where Cgc represents capacitance between the gate region (22) and the channel region (21), Cgt represents capacitance between the carrier confinement region (24) and the channel (21).
In conjunction with the mode shown in FIGS. 1A-1D for carrying out the invention, the inventors have found that the term C representing the capacitance between the carrier confinement region and the channel region in the expression (9) is most susceptible to the dispersion because the carrier confinement region is so implemented as to assume the carrier trap level. In order that the potential difference xcex94Vt mentioned above scarcely undergoes variation notwithstanding of variation in the capacitance C between the carrier confinement region and the channel region, the capacitance Cgt between the gate electrode and the channel region must be sufficiently smaller than the capacitance C (i.e., Cgt less than C).
Thus, according to another preferred mode for carrying out the invention, it is proposed to set at a small value the capacitance Cgt between the gate electrode (22) and the carrier confinement region (24) by interposing a gate insulation film (23) of a great thickness while setting at a large value the capacitance C between the carrier confinement region (24) and the channel region (21) by interposing therebetween an insulation film (25) of a small thickness.
On the other hand, in conjunction with the holding of data in the carrier confinement region (24), it is necessary to ensure stability against thermal fluctuations. At this juncture, let""s represent by Ctt the total capacitance existing between the carrier confinement region and all the other regions. In general, in the absolute temperature (T) system, energy fluctuation on the order of kT (where k represents Boltzmann""s constant and T represents temperature in degree Kelvin) will be unavoidable. Accordingly, in order to hold the data stably, it is required that change of energy given by q2/2Ctt as brought about by capturing a single electron is greater than the fluctuation mentioned above. To say in another way, the condition given by the following expression will have to be satisfied.
q2/2Ctt greater than kTxe2x80x83xe2x80x83(10) 
This condition requires that the total capacitance Ctt defined above has to be smaller than 3 aF inclusive in order to permit operation at a room temperature.
In still another mode for carrying out the invention as illustrated in FIGS. 17A and 17B of the accompanying drawings, a thin semiconductor film structure (48) is formed interiorly of an insulation film (49, 50) which is interposed between the storage region (47) and the channel region (46) with a view to reducing deterioration of the insulation film (49, 50).
Thus, in the semiconductor element implemented in accordance with the instant mode for carrying out the invention, a potential barrier provided by the thin film structure (48) is formed interiorly of the insulation film (49, 50) so that the thin film structure (48) plays effectively a same role as the insulation film, while making it possible to decrease the thickness of the insulation film in practical applications.
As can be seen in FIGS. 17A and 17B, the semiconductor thin film (48) provided internally of the insulation film (49, 50) has an energy level shifted by the conduction band under the effect of the quantum confinement effect in the direction thicknesswise of the semiconductor thin film and serves essentially as a potential barrier between the storage region and a carrier supply region for the write/erase operations, the reason of which will be elucidated below.
Representing the film thickness of the semiconductor thin film by L, effective mass of the carrier in the thin film by n and Planck""s constant by h, energy in the lowest energy state in quantum fluctuation of the carrier due to the confinement effect in the thicknesswise direction can appropriately be given by the following expression:
h2/8 mL2xe2x80x83xe2x80x83(11) 
In order that the energy shift due to the quantum confinement effect is made effective in consideration of the thermal energy fluctuation, the condition given by the following inequality expression (12) is required to be satisfied.
h2/8 mL2 greater than kTxe2x80x83xe2x80x83(12) 
In the light of the above expression (12), the thickness of the semiconductor thin film (48) formed of silicon (Si) will have to be smaller than 9 nm inclusive in order that the barrier is effective at a room temperature.
Thus, although there is a probability of the carrier existing in the semiconductor thin film for a short time upon moving of the carriers between the channel region (46) and the carrier confinement region (47) via the insulation film (49, 50), the probability of the carriers staying in the semiconductor thin film (48) for a long time is extremely low. As a result of this, the semiconductor thin film (48) operates as a temporary passage for the carriers upon migration thereof between the channel region (46) and the carrier confinement region (47), which means that the semiconductor thin film (48) will eventually serve as the potential barrier because of incapability of the carrier confining operation.
With the structure described above, the semiconductor element can exhibit the barrier effect with the insulation film of a smaller thickness when compared with the semiconductor element in which the above structure is not adopted. Thus, film fatigue of the insulation film (49, 50) can be suppressed. For further mitigating the film fatigue, the semiconductor thin film (48) may be formed in a multi-layer structure.
The structure in which the semiconductor thin film is provided in the insulation film can enjoy a further advantage that the height of the potential barrier between the carrier confinement region and the source region can properly be set. Since the energy shift due to the quantum confinement is determined in accordance with the size L of the carrier confinement region, it is possible to adjust the height of the barrier by adjusting the film thickness in addition to the selection of the thin film material. In this connection, it should be noted that in the semiconductor element of the structure known heretofore, the height of the barrier is determined only on the basis of the material constituting the insulation film.
The above other objects, features and attendant advantages of the present invention will more clearly be understood by reading the following description of the preferred embodiments thereof taken, only by way of example, in conjunction with the drawings.